The present invention relates to a drive voltage designed to sequentially energize a plurality of output lines, and more particularly to a drive voltage designed to sequentially energize the gate lines of a TFT liquid-crystal display.
FIG. 14 is a schematic block diagram depicting a common TFT (Thin Film Transistor) liquid-crystal display.
In FIG. 14, 1 is a TFT, 2 a liquid crystal, 3 a gate drive circuit, 4 a data drive circuit, and 5 a timing control circuit.
Pixel cells composed of TFTs 1 and liquid crystals 2 are arranged in a matrix at intersections between the gate lines of the gate drive circuits 3 and the data lines of the data drive circuits 4, as shown in FIG. 14.
As a switch for controlling the voltage applied to the liquid crystal of each pixel cell, each TFT 1 is switched on or off depending on the gate line drive signal OUTk (1xe2x89xa6kxe2x89xa6n) from the corresponding gate drive circuit 3. In an off-position, the liquid crystals and the data lines of the data drive circuits 4 are connected, and the voltage from the data lines is applied to the liquid crystals.
Each liquid crystal 2 is connected between a common terminal COM and the drain of a TFT 1 and is designed to vary light transmission in accordance with the voltage applied from the data line of the corresponding data drive circuit 4 via the TFT 1.
Each gate drive circuit 3 operates such that drive signals for sequentially energizing the gate lines connected to the TFT gates of each row of the pixel matrix are generated in accordance with the control signals from the timing control circuits 5. The TFTs of the pixel cells lying on the same line are switched on at the same time by the drive signals from the gate drive circuits 3.
The data drive circuits 4 are configured such that video signals Sc provided in synchronism with a horizontal sync signal are sequentially retained for each of the pixels of the pixel matrix in accordance with the control signals from the timing control circuits 5, and drive signals for energizing the data lines are generated in accordance with the video signals Sc of the pixels thus retained.
The timing control circuits 5 generate control signals whereby the video signals Sc of individual pixels are sequentially retained by the data drive circuits 4 on the basis of the horizontal or vertical sync signals of the video signals Sc. In addition, each gate drive circuit 3 generates a control signal for energizing the gate line with the timing (horizontal retrace periodicity) at which a video signal Sc corresponding to a single horizontal line is retained by the data drive circuit 4.
In a TFT liquid-crystal display thus configured, the video signals Sc presented to data drive circuits 4 are retained by each pixel of a horizontal line with a timing that corresponds to the control signals from the timing control circuits 5. The data lines corresponding to the pixels of the horizontal line are energized in accordance with the magnitude of the video signals Sc thus retained. Specific gate lines are energized with the timing that corresponds to the control signals from the timing control circuits 5, the TFTs of the pixel cells connected to these gate lines are switched on at the same time, and the drive voltage of each data line is applied to the liquid crystal. The applied voltage of each pixel cell is sequentially refreshed by repeating these operations for each horizontal line.
A conventional example of the gate drive circuit 3 shown in FIG. 14 will now be described.
FIG. 15 is a schematic block diagram illustrating an example of a conventional TFT gate drive circuit with three voltage levels. The circuit comprises 265 output channels designed to energize gate lines.
In FIG. 15, 6 is an input level shifting circuit, 8 a 265-bit bidirectional shift register circuit, 9 a decoding circuit, 10 an output level shifting circuit, and 11 an output buffer circuit.
The input level shifting circuit 6 allows the logic level of an input/output signal (between the power voltage VDD and the reference voltage VSS) to be shifted to the internal logic level of a gate drive circuit (between the power voltage VDL and the reference voltage VEE). Specifically, the levels of clock signals CPV, shift data STV1 and STV2, shift direction switching signals L/R, and other input/output signals are converted to the internal logic level of the gate drive circuit, and the input/output signals thus converted are presented to the bidirectional shift register 8 or decoding circuit 9.
The bidirectional shift register 8 operates such that the shift data STV1 (or shift data STV2) from the input level shifting circuit are sequentially shifted in synchronism with the clock signal CPV in the shifting direction that corresponds to the shift direction switching signals L/R. In addition, the shift data STV2 (or shift data STV1) shifted following the end bits of the shift register are sequentially presented to the input level shifting circuit 6.
The decoding circuit 9 generates three-bit data obtained by combining each bit of the bidirectional shift register 8 with the preceding and following bits, produces two-bit data for decoding shift direction switching signals L/R and selecting one of three voltage levels, and outputs the results to the output level shifting circuit 10 associated with the corresponding bits.
The output level shifting circuit 10 is a circuit whereby the signal level of the two-bit data obtained from the decoding circuit 9 is shifted to the high-voltage input signal level of the output buffer circuit 11. For example, the signal output from the decoding circuit 9, whose signal level is about 3 V in relation to the reference voltage VEE, is shifted by the output level shifting circuit 10 to a signal level of about 40 V and is presented to the output buffer circuit 11.
The output buffer circuit 11 operates such that one of three specific voltage levels is selected in accordance with the two-bit data obtained from the decoding circuit 9 via the output level shifting circuit 10, and the gate line is energized by a signal having the voltage level thus selected.
The operation of the TFT gate drive circuit thus configured (FIG. 15) will now be described with reference to FIGS. 16-18.
FIG. 16 is a diagram depicting the voltage level of an input/output signal and the voltage level of a gate line drive signal. Specific examples of such voltage levels are shown on the right side of the drawing.
For example, the internal reference voltage VEE may be set low (about 3-20 V in relation to the external reference voltage VSS) and the internal logic power voltage VDL may be set high (about 2.3-3.6 V in relation to the reference voltage VEE), as shown in FIG. 16. In addition, the power voltage VCOM and power voltage VL from the output buffer circuit 11 may be set such that, for example, the power voltage VCOM is about 10-30 V greater than the reference voltage VSS, and the power voltage VL is about 0-10.5 V greater than the reference voltage VEE.
FIG. 17 is a diagram depicting the waveform of the gate line drive signal with three voltage levels provided by the TFT gate drive circuit shown in FIG. 15.
The gate line drive signal from each output channel in a normal state is kept at the voltage level of the power voltage VL, as shown in FIG. 17. The voltage level of the gate line drive signal rises from the power voltage VL to the power voltage VCOM during the energizing of the gate line, and this voltage level is maintained for the duration of a single clock signal CPV, which is equal to the horizontal scanning period of a pixel signal. In the next horizontal scanning period, the voltage level decreases from the power voltage VCOM to the reference voltage VEE, and this voltage level is maintained for another horizontal scanning period. Such gate line drive signals are sequentially outputted from the output channels in synchronism with the clock signal CPV.
FIG. 18 is a diagram depicting the timing of the shift data and gate line drive signals in the TFT gate drive circuit shown in FIG. 15.
When shift data STV1 are fed to the input level shifting circuit 6, data related to the logic value of 1 and based on these shift data STV1 are latched onto a shift register SR1 during the rising of the clock signal CPV, as shown in FIG. 18. The data for the logic value of 1 are sequentially shifted from the shift register SR1 to the shift register SR265 in synchronism with the subsequent clock signal CPV.
A decoding circuit DEn (where n is an integer such that 2xe2x89xa6nxe2x89xa6265) generates two-bit data for selecting one of three voltage levels in accordance with the shift direction switching signal L/R and the data latched onto shift registers SRnxe2x88x921, SRn, and SRn+1.
In the example in which the gate line drive signal shown in FIG. 18 is generated, two-bit data are generated by the decoding circuit DEn, assuming that the output voltage level coincides with the power voltage VCOM when the shift register SRn is under conditions corresponding to the logic value of 1 and the shift register SRn+1 is under conditions corresponding to the logic value of 0, the output voltage level coincides with the reference voltage VEE when the shift register SRn is under conditions corresponding to the logic value of 0 and the shift register SRn+1 is under conditions corresponding to the logic value of 1, and the output voltage level coincides with the power voltage VL when the shift register SRn and the shift register SRn+1 are both under the conditions corresponding to the logic value of 0. It should be noted, however, that the aforementioned conditions correspond to a case in which the shift direction is set on the assumption that the shift data STV1 are inputted and the shift data STV2 are outputted, and the output voltage level is set based on the condition that the aforementioned shift register SRn+1 is re-read as a shift register SRnxe2x88x921 when the reverse shift direction is set.
An example in which the TFT gate drive circuit shown above in FIG. 15 is mounted on a semiconductor chip will now be described with reference to FIG. 19.
FIG. 19 is a diagram depicting a layout example of the TFT gate drive circuit shown in FIG. 15.
FIG. 19a is an overall layout drawing, and FIG. 19b is an expanded layout drawing of area A1 in FIG. 19a. 
Output channels OUT1-OUT58 and output channels OUT208-OUT265 for the gate line drive signal are arranged in a line in numerical order in the upper area of the chip in FIG. 19a, output channels OUT59-OUT207 are arranged in a line in numerical order in the lower area of the chip, and the circuit blocks of the output buffer circuit 11, output level shifting circuit 10, decoding circuit 9, and bidirectional shift register 8 corresponding to each output channel are disposed adjacent to the same area as the output channel in the manner shown in FIG. 19a. In addition, an input level shifting circuit 6 is disposed in the center of the upper area, and the output channels OUT1-OUT58 and output channels OUT208-OUT265 are disposed to the left and right thereof.
The shift register circuit SRn, decoding circuit DEn, output channel LSn, and output buffer circuit BFn, which constitute a circuit block associated with the n-th output channel, are disposed in the upper area in the direction from the lower side to the upper side of the chip in the order indicated, and in the lower area in the direction from the upper side to the lower side of the chip in the order indicated, as shown by the expanded layout diagram of FIG. 19b. In other words, the circuit blocks of the output channels are disposed as upper and lower halves symmetrical about the border between the upper area and the lower area.
Shift data STV1, which are inputted from the input level shifting circuit 6 in the center of the upper area to the shift register SR1 adjacent thereto on the right side thereof, are shifted to the right in order from shift register SR2 to shift register SR58, shifted from the shift register SR58 in the upper area to the shift register SR59 in the lower area, and then sequentially shifted to the left in order from shift register SR60 to shift register SR207, as shown by the dotted line in FIG. 19b. Although this is not shown in FIG. 19b, the data are shifted from the shift register SR207 to the shift register SR208, then shifted to the right in order from the shift register SR209 to the shift register SR265, and subsequently presented as shift data STV2 to the input level shifting circuit 6. The aforementioned shifting direction can be reversed in accordance with the shift direction switching signal L/R.
The shift data outputted from the input level shifting circuit 6 in the center of the upper area are thus sequentially shifted from the upper area to the lower area and are returned to the input level shifting circuit 6 in the upper area.
Drive ICs for liquid-crystal displays containing such gate line drive circuits are configured such that the number of circuit transistors tends to increase and the chips tend to become bigger with an increase in the number of pins needed to accommodate higher packaging density and in the number of horizontal lines needed to accommodate higher-quality pixels. Since increased chip size is accompanied by higher manufacturing costs, a need has long existed for minimizing the chip size in order to be able to manufacture less expensive drive ICs.
When, however, the output voltage level of the above-described TFT drive circuits reaches its maximum (about 40 V), the voltage thus produced is higher than the logic level (about 3 V), so transistors having higher withstand voltages and larger element dimensions in comparison with transistors having regular withstand voltages must be used for the output level shifting circuits, output buffer circuits, and other circuit blocks capable of handling such high voltages, creating the need to provide larger surface areas in order to accommodate these circuit blocks. It has been proposed to reduce the surface areas needed to accommodate such circuit blocks by, for example, reducing the number of transistors with high withstand voltages or reducing the element dimensions of such transistors, but these measures have largely been unsuccessful in providing cost reductions beyond those already achieved.
Another drawback is that devising circuit improvements and other measures aimed at achieving moderate reductions in the number of transistors in shift register circuits, decoding circuits, and other circuit blocks based on transistors with ordinary withstand voltages contributes only slightly to reducing the chip size because the surface areas occupied by such transistors are negligible in comparison with the surface areas occupied by transistors with high withstand voltages on such circuit blocks.
One aspect of the present invention, which was perfected in view of the above situation, is to provide a drive circuit whose size can be reduced with greater efficiency.
Aimed at attaining the stated aspect, the inventive drive circuit, which is designed to sequentially supply a drive voltage to a plurality of output lines, comprises a first shift register provided with m (where m is an integer of 2 or greater) serially connected bit circuits and designed to shift a drive data input away from the first bit circuit toward the m-th bit circuit on the basis of a clock signal in a first state, and to shift the drive data input away from the m-th bit circuit toward the first bit circuit on the basis of a clock signal in a second state; a first output circuit with m output units that correspond to the bit circuits of the first shift register and that present the first output line with a drive voltage based on data from the bit circuits in the first state; and a second output circuit with m output units that correspond to the bit circuits of the first shift register and that present the second output line with a drive voltage based on data from the bit circuits in the second state.
In addition, each output unit of the first output circuit presents the first output line with a first drive voltage as a nonselective drive voltage in the second state, and each output unit of the second output circuit presents the second output line with the first drive voltage as a nonselective drive voltage in the first state.
The drive circuit of the present invention may also comprise a second shift register provided with n (where n is an integer of 2 or greater) serially connected bit circuits and configured such that the data fed to the first bit circuit from the m-th bit circuit of the first shift register are shifted on the basis of a clock signal and fed from the n-th bit circuit to the m-th bit circuit of the first shift register; and a third output circuit with n output units that correspond to the bit circuits of the second shift register and that present the third output line with a drive voltage based on the data from the bit circuits.
The drive circuit of the present invention may also comprise a decoding circuit with m decoders that correspond to the bit circuits of the first shift register and that present the output unit of the first output circuit or the output unit of the second output circuit with a decoding signal for selecting a drive voltage on the basis of the data from the bit circuits.
It is also possible to use a structure in which each output unit of the first or second output circuit presents the first or second output line with a drive voltage selected from the first drive voltage as a nonselective drive voltage based on the decoding signal, a second drive voltage as a selective drive voltage, and a third drive voltage as a nonselective drive voltage.